WhizniumDBE Reference
Overview
Scope
Model-based description
Source code tree iteration
Development workflow
Module templates
Architectural features
top module (top_v1_0)
Parameters
Ports
host interface (hostif_Easy_v1_0)
Parameters
Generics
Ports
memory-mapped AXI co-host interface (aximmcohostif_Easy_v1_0)
Parameters
Ports
co-host interface (cohostif_Easy_v1_0)
Parameters
Generics
Ports
Simple interfaces
AXI slave (axislave_v1_0)
Generics
Ports
SPI slave (spislave_v2_0)
Generics
Ports
UART receiver (uartrx_v2_0)
Generics
Ports
UART transmitter (uarttx_v2_0)
Generics
Ports
GPIO controller (gpio_Easy_v1_0)
Parameters
Ports
I2C master (i2c_Easy_v1_0)
Parameters
Generics
Ports
UART controller (uart_Easy_v1_0)
Generics
Ports
Helpers
BCD frequency generator (bcdfreq_v1_0)
Generics
Ports
CRC calculator (crcspec_v3_0)
Parameters
Generics
Ports
de-bouncer (debounce_v1_0)
Generics
Ports
neo random number generator (neotrng_v1_0)
Generics
Ports
time-out counter (timeout_v1_0)
Generics
Ports
version identification (ident_Easy_v1_0)
Parameters
10 kHz clock source (tkclksrc_Easy_v1_0)
Generics
Ports
AXI stream helpers
AXI stream FIFO (axisfifo_v1_0)
Generics
Ports
sparse AXI stream forwarder (sprsaxisfwd_v1_0)
Generics
Ports
Design probing
FSM probe (fsmprobe_Easy_v1_0)
Generics
Ports
FSM state tracker (fsmtrack_Easy_v1_0)
Parameters
Ports
General-purpose signal tracker (gptrack_Easy_v1_0)
Parameters
Ports
Advanced functionality
MIPI receiver (mipirx_v1_0)
PCI express endpoint (pcie_v1_0)
DDR memory multiplexer (ddrmux_Easy_v1_0)
Parameters
Ports
Device drivers
128x32 OLED display (oled128x32_v1_0)
Generics
Ports
RGB LED (rgbled_v1_0)
Generics
Ports
Vendor IP wrappers
Efinix
Lattice
Microchip
Xilinx
MCU-related
Database structure
Administration / global
Project management
Modular structure
High-level features
Fine structure
Import/export structure
Initialization data
Projects and versions
Modular structure
Command set
Data flows and algorithms
Fine structure
Deployment information
Glossary of terms
WhizniumDBE Reference
Import/export structure
Data flows and algorithms
View page source
Data flows and algorithms