Whiznium CV Demonstrator
Overview
Setup
Setting up the Whiznium Computer Vision Demonstrator project (workstation, all variants)
AMD MPSoC / ZU Board variant: running the Vivado design flow
AMD MPSoC / ZU Board variant: creating the zuvsp IP core in Vivado from scratch
Efinix Titanium devkit variant: running the Efinity design flow
Efinix Titanium devkit variant: creating the tivsp IP core in Efinity from scratch
Microchip PolarFire SoC Disco kit variant: running the Libero SoC design flow
Microchip PolarFire SoC Disco kit: creating the dcvsp IP core in Libero SoC from scratch
Examples
FPGA-based turntable positioning commanded from CPU
FPGA-based image decimation, CPU readout via AXIlite and display in web UI
FPGA-based full-frame HDR image calculation in shared DDR memory space
IP cores for vendor-agnostic design probing
Whiznium CV Demonstrator
Examples
FPGA-based turntable positioning commanded from CPU
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FPGA-based turntable positioning commanded from CPU